AMD Xilinx
XC6VCX195T-2FF1156I
XC6VCX195T-2FF1156I ECAD Model
XC6VCX195T-2FF1156I Attributes
| Type | Description | Select |
|---|---|---|
| Pbfree Code | No | |
| Rohs Code | No | |
| Part Life Cycle Code | Active | |
| Supply Voltage-Nom | 1 V | |
| Number of Inputs | 600 | |
| Number of Outputs | 600 | |
| Number of Logic Cells | 199680 | |
| Number of CLBs | 15600 | |
| Combinatorial Delay of a CLB-Max | 910 ps | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Package Shape | SQUARE | |
| Technology | CMOS | |
| Clock Frequency-Max | 1.098 GHz | |
| Power Supplies | 1,1.2/2.5,2.5 V | |
| Supply Voltage-Max | 1.05 V | |
| Supply Voltage-Min | 950 mV | |
| JESD-30 Code | S-PBGA-B1156 | |
| Qualification Status | Not Qualified | |
| JESD-609 Code | e0 | |
| Moisture Sensitivity Level | 4 | |
| Operating Temperature-Max | 100 °C | |
| Operating Temperature-Min | -40 °C | |
| Peak Reflow Temperature (Cel) | 225 | |
| Time@Peak Reflow Temperature-Max (s) | 30 | |
| Number of Terminals | 1156 | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | BGA | |
| Package Equivalence Code | BGA1156,34X34,40 | |
| Package Shape | SQUARE | |
| Package Style | GRID ARRAY | |
| Surface Mount | YES | |
| Terminal Finish | TIN LEAD | |
| Terminal Form | BALL | |
| Terminal Pitch | 1 mm | |
| Terminal Position | BOTTOM | |
| Width | 35 mm | |
| Length | 35 mm | |
| Seated Height-Max | 3.5 mm | |
| Ihs Manufacturer | XILINX INC | |
| Part Package Code | BGA | |
| Package Description | 35 X 35 MM, FBGA-1156 | |
| Pin Count | 1156 | |
| Reach Compliance Code | not_compliant | |
| ECCN Code | 3A991.D | |
| HTS Code | 8542.39.00.01 |
XC6VCX195T-2FF1156I Datasheet Download
XC6VCX195T-2FF1156I Overview
The chip model XC6VCX195T-2FF1156I is a powerful and versatile chip model developed by Xilinx, Inc. It is designed to meet the demands of a wide range of applications, including communication, automotive, industrial, and consumer electronics. The chip model is based on the Xilinx Virtex-6 FPGA family and provides the highest performance and power efficiency available in the market.
The XC6VCX195T-2FF1156I chip model is designed to provide a high-performance, low-power solution for a variety of applications. It features a high-performance, low-power, low-cost FPGA architecture with advanced features such as high-speed transceivers, low-power clock management, and advanced memory controllers. It also features a range of advanced features such as high-speed I/O, high-speed serial transceivers, and a variety of memory controllers that enable the chip model to be used in a wide range of applications.
The chip model is designed to provide a high-performance, low-power solution for a variety of applications. It features a low-power, low-cost FPGA architecture and advanced features such as high-speed transceivers, low-power clock management, and advanced memory controllers. The XC6VCX195T-2FF1156I chip model is also designed to be highly reliable, with a wide range of features such as advanced error correction, data integrity, and error detection.
The XC6VCX195T-2FF1156I chip model is designed to provide a high-performance, low-power solution for a variety of applications. It is expected to be in high demand in the future, as more and more applications require high-performance, low-power solutions. The chip model is also expected to be used in advanced communication systems, as it is designed to be highly reliable and to support advanced features such as high-speed transceivers and low-power clock management.
The chip model is designed to be highly reliable and to support advanced features such as high-speed transceivers and low-power clock management. The XC6VCX195T-2FF1156I chip model is also designed to be upgradeable, so that it can be used in future applications that require higher performance and power efficiency. The chip model is also designed to be flexible, so that it can be used in a variety of applications and environments.
In conclusion, the XC6VCX195T-2FF1156I chip model is a powerful and versatile chip model developed by Xilinx, Inc. It is designed to provide a high-performance, low-power solution for a variety of applications. It features a low-power, low-cost FPGA architecture and advanced features such as high-speed transceivers, low-power clock management, and advanced memory controllers. It is expected to be in high demand in the future, as more and more applications require high-performance, low-power solutions. The chip model is also designed to be upgradeable, so that it can be used in future applications that require higher performance and power efficiency. Finally, the chip model is designed to be flexible, so that it can be used in a variety of applications and environments.
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