EP20K100BI356-3
EP20K100BI356-3
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rohs

Intel Corporation

EP20K100BI356-3


EP20K100BI356-3
F18-EP20K100BI356-3
Active
IC FPGA 252 I/O 356BGA
356-BGA (35x35)

EP20K100BI356-3 ECAD Model


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EP20K100BI356-3 Attributes


Type Description Select
Rohs Code No
Part Life Cycle Code Transferred
Supply Voltage-Nom 2.5 V
Number of Inputs 246
Number of Outputs 246
Number of Logic Cells 4160
Number of Dedicated Inputs 4
Number of I/O Lines 252
Programmable Logic Type LOADABLE PLD
Package Shape SQUARE
Technology CMOS
Organization 4 DEDICATED INPUTS, 252 I/O
Output Function MACROCELL
Power Supplies 2.5,2.5/3.3 V
Supply Voltage-Max 2.625 V
Supply Voltage-Min 2.375 V
JESD-30 Code S-PBGA-B356
Qualification Status Not Qualified
JESD-609 Code e0
Peak Reflow Temperature (Cel) 220
Number of Terminals 356
Package Body Material PLASTIC/EPOXY
Package Code LBGA
Package Equivalence Code BGA356,26X26,50
Package Shape SQUARE
Package Style GRID ARRAY, LOW PROFILE
Surface Mount YES
Terminal Finish TIN LEAD
Terminal Form BALL
Terminal Pitch 1.27 mm
Terminal Position BOTTOM
Width 35 mm
Length 35 mm
Seated Height-Max 1.63 mm
Ihs Manufacturer ALTERA CORP
Part Package Code BGA
Package Description LBGA, BGA356,26X26,50
Pin Count 356
Reach Compliance Code compliant
ECCN Code 3A991.D
HTS Code 8542.39.00.01

EP20K100BI356-3 Overview



The chip model EP20K100BI356-3 is a high-performance, low-power field programmable gate array (FPGA) device developed by Altera Corporation. It is a member of the Stratix II family of FPGAs, and is designed to improve the performance of system designs. This model is designed to be used in a wide range of applications, including communications, networking, industrial, automotive, and aerospace.


The EP20K100BI356-3 chip model has several advantages over other FPGA models. It has a large capacity, with up to 20,000 logic elements and up to 25,000 memory bits. It also features dynamic partial reconfiguration, which allows parts of the chip to be reconfigured without having to shut down the entire system. Additionally, it has a high-speed transceiver, which allows for high-speed data transfer.


In terms of future development trends, the EP20K100BI356-3 chip model is expected to be used in a variety of applications, such as wireless communication, automotive, industrial, and aerospace. It is also expected to be used in advanced communication systems, such as 5G and beyond. This is due to its high-speed transceiver, which allows for data transfer at high speeds. Additionally, its dynamic partial reconfiguration feature makes it suitable for applications that require flexibility and scalability.


The original design intention of the EP20K100BI356-3 chip model was to provide a high-performance, low-power FPGA solution for a wide range of applications. It was designed to be used in systems that require high-speed data transfer, as well as flexibility and scalability. As technology advances, it is possible that the chip model may require upgrades in order to remain compatible with the latest technologies.


In conclusion, the EP20K100BI356-3 chip model is a high-performance, low-power field programmable gate array device that is designed to be used in a wide range of applications. It has several advantages, such as a large capacity, dynamic partial reconfiguration, and a high-speed transceiver, which make it suitable for advanced communication systems. It is expected to be used in a variety of applications in the future, and may require upgrades in order to remain compatible with the latest technologies.



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