
Lattice Semiconductor Corporation
LCMXO3LF-1300E-5UWG36CTR50
LCMXO3LF-1300E-5UWG36CTR50 ECAD Model
LCMXO3LF-1300E-5UWG36CTR50 Attributes
Type | Description | Select |
---|---|---|
Mfr | Lattice Semiconductor Corporation | |
Series | MachXO3 | |
Package | Tape & Reel (TR) | |
Number of LABs/CLBs | 160 | |
Number of Logic Elements/Cells | 1280 | |
Total RAM Bits | 65536 | |
Number of I/O | 28 | |
Voltage - Supply | 1.14V ~ 1.26V | |
Mounting Type | Surface Mount | |
Operating Temperature | 0°C ~ 85°C (TJ) | |
Package / Case | 36-UFBGA, WLCSP | |
Supplier Device Package | 36-WLCSP (2.54x2.59) |
LCMXO3LF-1300E-5UWG36CTR50 Datasheet Download
LCMXO3LF-1300E-5UWG36CTR50 Overview
The LCMXO3LF-1300E-5UWG36CTR50 is a low-cost, low-power field-programmable gate array (FPGA) chip from Lattice Semiconductor.
The chip is based on the Lattice ECP3 FPGA architecture and features a 1300K logic element (LE) count, 5.5Mb of embedded memory, and up to 2,400 6-input look-up tables (LUTs). It has a maximum operating frequency of up to 250MHz and a maximum I/O count of 160. Additionally, the chip features a 3.3V single supply voltage, a 0.8V core voltage, and a -40°C to +85°C temperature range.
The LCMXO3LF-1300E-5UWG36CTR50 is ideal for a variety of applications, such as those requiring low-power, low-cost, and high-performance solutions. It is suitable for embedded systems, industrial automation, consumer electronics, and automotive applications.
The chip also offers a wide range of features, such as non-volatile configuration memory, an integrated phase-locked loop (PLL), and a wide range of I/O standards. It also supports a variety of design tools, including the Lattice Diamond design suite and the Lattice Diamond Programmer.
In summary, the LCMXO3LF-1300E-5UWG36CTR50 is a low-cost, low-power FPGA chip from Lattice Semiconductor that is suitable for a wide range of applications. It features a 1300K logic element count, 5.5Mb of embedded memory, and up to 2,400 6-input LUTs, as well as a wide range of features such as non-volatile configuration memory and an integrated PLL.
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