
AMD Xilinx
XCV812E-8BGG560I
XCV812E-8BGG560I ECAD Model
XCV812E-8BGG560I Attributes
Type | Description | Select |
---|---|---|
Pbfree Code | Yes | |
Rohs Code | Yes | |
Part Life Cycle Code | Obsolete | |
Supply Voltage-Nom | 1.8 V | |
Number of Equivalent Gates | 254016 | |
Number of CLBs | 4704 | |
Combinatorial Delay of a CLB-Max | 400 ps | |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
Temperature Grade | INDUSTRIAL | |
Package Shape | SQUARE | |
Technology | CMOS | |
Organization | 4704 CLBS, 254016 GATES | |
Clock Frequency-Max | 416 MHz | |
Supply Voltage-Max | 1.89 V | |
Supply Voltage-Min | 1.71 V | |
JESD-30 Code | S-PBGA-B560 | |
Qualification Status | Not Qualified | |
JESD-609 Code | e1 | |
Moisture Sensitivity Level | 3 | |
Operating Temperature-Max | 85 °C | |
Operating Temperature-Min | -40 °C | |
Peak Reflow Temperature (Cel) | 260 | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Number of Terminals | 560 | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | LBGA | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY, LOW PROFILE | |
Surface Mount | YES | |
Terminal Finish | Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) | |
Terminal Form | BALL | |
Terminal Pitch | 1.27 mm | |
Terminal Position | BOTTOM | |
Width | 42.5 mm | |
Length | 42.5 mm | |
Seated Height-Max | 1.7 mm | |
Ihs Manufacturer | XILINX INC | |
Part Package Code | BGA | |
Package Description | LBGA, | |
Pin Count | 560 | |
Reach Compliance Code | compliant | |
HTS Code | 8542.39.00.01 |
XCV812E-8BGG560I Datasheet Download
XCV812E-8BGG560I Overview
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Overall, the XCV812E-8BGG560I model is a revolutionary chip model that has the potential to revolutionize the way we work and interact with technology. It is designed to provide users with the highest levels of performance, security, and scalability, making it an ideal choice for a variety of applications. Additionally, the model is expected to be in high demand in the near future, as it is designed to be used in a variety of networks and intelligent scenarios. Finally, the model is expected to be used in the era of fully intelligent systems, as it is designed to provide users with the highest levels of performance, security, and scalability.
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