LFE2M35E-6FN484C

The LFE2M35E-6FN484C is a low-power, low-cost field-programmable gate array (FPGA) chip from Lattice Semiconductor. It is a member of the Lattice MachXO2 family of FPGAs and is based on the MachXO2-1200 device architecture. The chip has an array of programmable logic blocks, memory blocks and digital signal processing blocks, which can be configured to perform various tasks.

The LFE2M35E-6FN484C has a total of 4,096 logic cells, 4,096 flip-flops, and 4,096 bits of RAM, as well as two dedicated PLLs for clock management. It also has two dedicated I/O banks, with up to 48 I/O pins per bank, and a total of 48 I/O pins. It is designed to operate at a maximum speed of 250 MHz and consumes a maximum of 1.8 W of power.

The LFE2M35E-6FN484C is suitable for a wide range of applications, including embedded systems, industrial control, medical devices, automotive, and consumer electronics. It enables designers to implement complex functions in a small form factor, with low power consumption and low cost. It is also suitable for high-speed data processing, signal processing, and image processing applications. It is available in a 4.9 mm x 4.9 mm RoHS-compliant package, and is supported by the Lattice Diamond software suite.