ISPLSI 2128VE-180LT100
ISPLSI 2128VE-180LT100
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rohs

Lattice Semiconductor Corporation

ISPLSI 2128VE-180LT100


ISPLSI 2128VE-180LT100
F11-ISPLSI 2128VE-180LT100
Active
IC CPLD 128MC 5NS 100TQFP
100-TQFP (14x14)

ISPLSI 2128VE-180LT100 ECAD Model


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ISPLSI 2128VE-180LT100 Attributes


Type Description Select
Mfr Lattice Semiconductor Corporation
Series ispLSI® 2000VE
Package Tray
Programmable Type In System Programmable
Delay Time tpd(1) Max 5 ns
Voltage Supply - Internal 3V ~ 3.6V
Number of Logic Elements/Blocks 32
Number of Macrocells 128
Number of Gates 6000
Number of I/O 64
Operating Temperature 0°C ~ 70°C (TA)
Mounting Type Surface Mount
Package / Case 100-LQFP
Supplier Device Package 100-TQFP (14x14)
Base Product Number ISPLSI 2128VE

ISPLSI 2128VE-180LT100 Datasheet Download


ISPLSI 2128VE-180LT100 Overview



The ISPLSI 2128VE-180LT100 is a programmable logic device (PLD) manufactured by Lattice Semiconductor. It is a high-density, low-cost, low-power, high-performance device designed for a wide range of applications. It is a single-chip, non-volatile, electrically erasable programmable logic device (EEPLD).


The ISPLSI 2128VE-180LT100 has a 180-pin TQFP package and is capable of supporting up to 128 macrocells and up to 8192 bits of embedded memory. It is an ideal device for applications that require high-density logic and memory resources. It has a total power dissipation of 1.8W, and a maximum operating frequency of up to 100MHz.


The ISPLSI 2128VE-180LT100 is a cost-effective solution for a variety of applications such as embedded controllers, data acquisition systems, communication systems, industrial control systems, and automotive applications. It supports a wide range of features such as programmable logic array (PLA), programmable logic array (PLA) with embedded memory, and look-up table (LUT). It also has a built-in phase locked loop (PLL) for clock synthesis and a low-jitter clock output.


In addition, the ISPLSI 2128VE-180LT100 is designed to be compatible with the Lattice Diamond design software and the Lattice ispLEVER Classic design software. It is also compatible with the IEEE 1149.1 (JTAG) boundary-scan architecture. The device is also RoHS compliant and is available in a variety of packages.



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