
Intel Corporation
EP20K200EBC652-2
EP20K200EBC652-2 ECAD Model
EP20K200EBC652-2 Attributes
Type | Description | Select |
---|---|---|
Rohs Code | No | |
Part Life Cycle Code | Obsolete | |
Supply Voltage-Nom | 1.8 V | |
Propagation Delay | 1.97 ns | |
Number of Inputs | 368 | |
Number of Outputs | 368 | |
Number of Logic Cells | 8320 | |
Number of Dedicated Inputs | 4 | |
Number of I/O Lines | 376 | |
Programmable Logic Type | LOADABLE PLD | |
Temperature Grade | OTHER | |
Package Shape | SQUARE | |
Technology | CMOS | |
Organization | 4 DEDICATED INPUTS, 376 I/O | |
Output Function | MACROCELL | |
Power Supplies | 1.8,1.8/3.3 V | |
Supply Voltage-Max | 1.89 V | |
Supply Voltage-Min | 1.71 V | |
JESD-30 Code | S-PBGA-B652 | |
Qualification Status | Not Qualified | |
JESD-609 Code | e0 | |
Moisture Sensitivity Level | 3 | |
Operating Temperature-Max | 85 °C | |
Peak Reflow Temperature (Cel) | 220 | |
Number of Terminals | 652 | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | BGA | |
Package Equivalence Code | BGA652,35X35,50 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY | |
Surface Mount | YES | |
Terminal Finish | TIN LEAD | |
Terminal Form | BALL | |
Terminal Pitch | 1.27 mm | |
Terminal Position | BOTTOM | |
Width | 45 mm | |
Length | 45 mm | |
Seated Height-Max | 3.5 mm | |
Ihs Manufacturer | ALTERA CORP | |
Package Description | BGA, BGA652,35X35,50 | |
Reach Compliance Code | compliant | |
ECCN Code | 3A991.D | |
HTS Code | 8542.39.00.01 | |
Part Package Code | BGA | |
Pin Count | 652 |
EP20K200EBC652-2 Overview
The chip model EP20K200EBC652-2 is a high-performance, low-power field programmable gate array (FPGA) designed by Altera Corporation. It is suitable for a wide range of applications, including high-performance digital signal processing, embedded processing, image processing, and more. It is an ideal choice for applications that require high speed and low power consumption.
The EP20K200EBC652-2 has a wide range of features and capabilities, including a large number of logic elements, high-speed memory, and a wide range of I/O options. It is capable of supporting a variety of HDL languages, including Verilog, VHDL, and more. The chip model also has an integrated JTAG interface, allowing for easy debugging and programming.
The EP20K200EBC652-2 is an ideal choice for applications that require high-performance processing and low power consumption. It can be used for a variety of applications, including digital signal processing, embedded processing, image processing, and more. It is also suitable for the development and popularization of future intelligent robots.
Using the chip model EP20K200EBC652-2 effectively requires a certain level of technical knowledge and skill. It is important to understand the product description and design requirements of the chip model. In addition, it is also important to be familiar with the HDL languages used to program the chip model. It is also beneficial to have experience with the JTAG interface, as this can be used for debugging and programming.
To ensure the successful use of the EP20K200EBC652-2 chip model, it is important to take into account the actual case studies and precautions. It is also important to take into account the power consumption, temperature, and other environmental factors that may affect the performance of the chip model.
In conclusion, the chip model EP20K200EBC652-2 is a powerful and low-power FPGA designed by Altera Corporation. It is suitable for a wide range of applications, including high-performance digital signal processing, embedded processing, image processing, and more. It is also suitable for the development and popularization of future intelligent robots. Using the chip model effectively requires a certain level of technical knowledge and skill, and it is important to take into account the actual case studies and precautions.
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