EPF10K130VGC599-2
EPF10K130VGC599-2
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rohs

Altera Corporation

EPF10K130VGC599-2


EPF10K130VGC599-2
F53-EPF10K130VGC599-2
Active
LOADABLE PLD, 500 ps, CMOS, IPGA, SPGA599,47X47
IPGA, SPGA599,47X47

EPF10K130VGC599-2 ECAD Model


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EPF10K130VGC599-2 Attributes


Type Description Select
Pbfree Code No
Rohs Code No
Part Life Cycle Code Obsolete
Supply Voltage-Nom 3.3 V
Propagation Delay 500 ps
Number of Inputs 470
Number of Outputs 466
Number of Logic Cells 832
Number of Dedicated Inputs 4
Number of I/O Lines 470
Programmable Logic Type LOADABLE PLD
Temperature Grade COMMERCIAL
Package Shape SQUARE
Technology CMOS
Organization 4 DEDICATED INPUTS, 470 I/O
Output Function REGISTERED
Power Supplies 3.3 V
Supply Voltage-Max 3.6 V
Supply Voltage-Min 3 V
JESD-30 Code S-CPGA-P599
Qualification Status Not Qualified
JESD-609 Code e0
Moisture Sensitivity Level 1
Operating Temperature-Max 70 °C
Peak Reflow Temperature (Cel) 220
Number of Terminals 599
Package Body Material CERAMIC, METAL-SEALED COFIRED
Package Code IPGA
Package Equivalence Code SPGA599,47X47
Package Shape SQUARE
Package Style GRID ARRAY, INTERSTITIAL PITCH
Surface Mount NO
Terminal Finish TIN LEAD
Terminal Form PIN/PEG
Terminal Pitch 2.54 mm
Terminal Position PERPENDICULAR
Width 62.484 mm
Length 62.484 mm
Seated Height-Max 5.08 mm
Ihs Manufacturer ALTERA CORP
Package Description IPGA, SPGA599,47X47
Reach Compliance Code unknown
HTS Code 8542.39.00.01
Part Package Code PGA
Pin Count 599
ECCN Code 3A991.D

EPF10K130VGC599-2 Datasheet Download


EPF10K130VGC599-2 Overview



The chip model EPF10K130VGC599-2 is a powerful and versatile digital signal processor (DSP) designed for high-performance digital signal processing, embedded processing, and image processing. It is based on an advanced and flexible architecture, and its main components are an array of digital logic blocks, a programmable interconnect, and embedded memory blocks. This chip model is designed to be programmed with HDL (Hardware Description Language) and can be used to develop applications such as digital signal processing, embedded processing, image processing, and more.


The original design intention of the chip model EPF10K130VGC599-2 was to provide a versatile and powerful platform for developers to create high-performance applications. It is also designed to be easily upgradable, so it can be used to develop applications for more advanced communication systems. Its flexibility and scalability also make it suitable for use in a variety of applications, including those related to the development and popularization of future intelligent robots.


To use the chip model EPF10K130VGC599-2 effectively, one must possess a good understanding of HDL (Hardware Description Language). A thorough knowledge of this language is necessary to develop applications for the chip, so it is important for those who wish to use this chip model to have a good understanding of HDL. Additionally, it is important to have a good understanding of the architecture of the chip model, as well as the capabilities of the various components of the chip. This will enable developers to create applications that can take full advantage of the chip model's capabilities.



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Unit Price: $359.6469
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Pricing (USD)

QTY Unit Price Ext Price
1+ $334.4716 $334.4716
10+ $330.8751 $3,308.7515
100+ $312.8928 $31,289.2803
1000+ $294.9105 $147,455.2290
10000+ $269.7352 $269,735.1750
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